NVIDIA CEO Jensen Huang's recent comments on Huawei's semiconductor technology have sparked discussion. Following a dinner with supply chain partners in Taipei, Taiwan, China, Huang was asked about Huawei's "Tau (τ) Law" and "logic folding" technology. He offered a seemingly dismissive assessment, stating it was a breakthrough for Huawei but not a threat to Taiwan Semiconductor Manufacturing (TSM), as TSMC has been using chip stacking and 3D packaging for nearly a decade.
This evaluation, while appearing fair, is based on a fundamental misunderstanding. Huang equated Huawei's logic folding with the 3D packaging technology TSMC has developed over the past ten years. The implication was that Huawei's efforts are merely catching up to older TSMC technology. However, logic folding and traditional 3D packaging are fundamentally different technologies.
Examining what Huawei has achieved clarifies the distinction. Logic folding, a core technology of the Tau Law, involves folding and vertically interconnecting circuits that are traditionally laid out on a two-dimensional plane into a three-dimensional stack. This reduces critical path wire lengths by 50% to 80%, significantly lowering signal propagation RC load.
This might sound like simply "stacking chips," but the reality is far more nuanced. The core difference lies at an essential level: 2.5D/3D packaging focuses on connecting already fabricated, independent dies. Logic folding focuses on re-arranging the logic gates *within* a single die. In simpler terms, the former brings different chips closer together during the manufacturing stage, while the latter fundamentally shortens the physical distance signals must travel during the design phase. Logic folding changes "how far the signal itself must travel," whereas 2.5D/3D packaging only changes "how close different chips are to each other."
This signifies that logic folding is essentially a circuit topology reconstruction at the chip design level, acting on the vertical integration of logic layers within a single chip. Advanced packaging belongs to the manufacturing process level as a multi-chip interconnection technology. They operate at completely different levels of technical abstraction, solving problems in different dimensions.
An analogy helps illustrate this. Traditional 2.5D packaging is like moving two separate rooms to the same floor and building a corridor (a silicon interposer) between them. 3D packaging goes further, stacking two separate buildings and installing elevators (Through-Silicon Vias, TSVs) for access. Regardless, components like HBM and the GPU remain separate buildings—physically distinct chips.
Logic folding, however, is akin to designing the internal layout of a single building. It places two rooms that need frequent communication—originally at opposite ends—directly on top of each other, one on the first floor and one directly above. There's no need for long corridors or elevator shafts, just an extremely short vertical channel (an ultra-short TSV with a pitch of only 1.5 micrometers). This is a difference in "design philosophy," not merely "construction method."
Research from Peking University's School of Integrated Circuits elaborates on this distinction, proposing a paradigm division between "true 3D" and "pseudo-3D." Pseudo-3D assigns entire modules as the minimum unit to a specific die, with all standard cells within a module confined to the same die. True 3D allows free partitioning within a module, enabling standard cells from the same module to be distributed across different dies, offering a larger design space. In terms of optimization, pseudo-3D optimizes on each die separately, heavily reusing traditional 2D chip EDA tools and prohibiting operations like cross-die logic transformation or movement. True 3D treats the combined space of multiple dies as the design space, conducting search and optimization in a complete three-dimensional design space across all design stages without restricting cross-die operations.
Logic folding advances the minimum unit of physical implementation from the "die" to "the three-dimensional position of a standard cell." This represents a genuine paradigm shift at the foundational level. TSMC's advanced packaging technologies like CoWoS and SoIC are excellent, but their subject is multiple independently manufactured dies. Logic folding's subject is the combinational logic gates *within* a single die. One is about "packing pre-made building blocks more tightly"; the other is about "considering how the block itself can stand more stably during its shape design."
This distinction appears overlooked in Huang's comments. By categorizing logic folding as "chip stacking and 3D packaging technology" and claiming TSMC had it a decade ago, he implicitly places Huawei's technology and TSMC's foundry capabilities on the same track for comparison, concluding the "competitor isn't as fast."
The issue is, they are not on the same track.
Another layer of difference involves dependency. The performance advantages of advanced packaging are deeply tied to and must be fully leveraged with advanced process nodes. For instance, TSMC's CoWoS packaging is co-designed with its N2 2nm process; the absence of either significantly diminishes returns. Huawei's core breakthrough with logic folding is that, without substantially changing the existing process node, it achieves a 55% increase in transistor density per generation solely through design innovation. In the traditional Moore's Law path, such progress would require two full process node iterations, taking approximately three years.
The upcoming Huawei Kirin 2026 chip serves as proof. Compared to the Kirin 9030 Pro, the Kirin 2026's transistor density increases by 53.5% to 238 MTr/mm². This means 238 million transistors can be integrated per square millimeter of chip area, theoretically on par with Intel's 18A process and close to TSMC's first-generation 3nm. Simultaneously, the SoC performance core's energy efficiency improves by 41%, with the maximum frequency increasing by nearly 13%. These gains are not from shrinking line widths or changing processes but are "squeezed out" at the design level.
Importantly, this is just the beginning. Huawei's He Tingbo has outlined a clear roadmap: from 2026 to 2031, following the Tau Law path, transistor density will continue to rise, projected to exceed 400 MTr/mm² by 2031, with CPU big core frequencies surpassing 5GHz.
By then, the transistor density metrics of high-end chips based on the Tau Law could match those of a 1.4nm chip process. In other words, a technology path not reliant on EUV or geometric scaling could, within five years, reach performance levels comparable to the most advanced processes today. Is TSMC a decade ahead? If viewed from the perspective of this new "design philosophy" track, the answer is less certain.
This path is undoubtedly challenging. The full realization of the Tau Law requires far more than the efforts of a single chip design company. As He Tingbo candidly stated, numerous open problems exist that no single organization can solve independently—cross-disciplinary collaboration is needed for toolchains, standards, benchmarks, device physics, and economic models.
The toughest challenge is the EDA toolchain. Traditional 2D design flows and current "pseudo-3D" flows are insufficient to harness logic folding's potential. To truly implement it, physical design must search within a complete 3D space, with intra-module partitioning, cross-die interconnection, and vertical thermal path optimization co-optimized within a unified framework.
Progress is being made. Peking University's School of Integrated Circuits has developed a prototype "true 3D" physical implementation EDA tool for logic folding, covering placement planning and placement stages, and supporting tens of millions of instances via GPU acceleration. Compared to the most representative pseudo-3D design flow, this tool achieves an average wire length reduction of about 30% and significant timing improvements, with peak temperatures dropping over 3% on average when joint thermal optimization is enabled.
The core idea of the Tau Law is essentially a paradigm revolution from "geometric thinking" to "systems thinking." He Tingbo's paper outlines four levels of τ: picoseconds at the transistor level, nanoseconds at the circuit level, microseconds at the chip level, and seconds at the system/data center level. The Tau Law's essence is bringing everyone to the same ledger—accounting entirely in units of time. The five picoseconds saved by a process expert carry the same weight in the total ledger as the five picoseconds saved by an architect or software expert. Previously, foundries focused on shrinking transistors, circuit designers on routing, and software engineers on coding, all speaking different languages. The τ Law forcibly breaks down the barriers between these levels.
This is precisely the kind of foundational mindset shift needed in the semiconductor industry. Huang's misinterpretation reflects a broader cognitive bias: steeped in the old paradigm of Moore's Law for too long, many are accustomed to judging everything by "geometric size" and "packaging form." The Tau Law suggests changing the ruler.
As the红利 of geometric scaling nears its end and the cost of advanced processes becomes prohibitively high, Huawei proposes a path of using "systems engineering integration capability" to hedge against "individual chip process shortcomings." Trading space-time for geometry, winning with systems over individual points. This is not about trying to surpass TSMC on TSMC's track but striving to change lanes for overtaking.
Huang stated "TSMC is a decade ahead," which holds true if one only looks at 3D packaging at the manufacturing process level. But logic folding is not 3D packaging; it is an innovation at the design philosophy level. Comparing two technologies at completely different levels of abstraction and declaring one a decade ahead of the other is a category error. Or, to put it more bluntly: Huang likely did not thoroughly read He Tingbo's paper on the subject.
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