DeepSeek shook the semiconductor industry and the stock market with the release of its R1 reasoning model. R1 matched top-tier models like OpenAI’s o1, yet it was reportedly trained for a fraction of the cost, around $6 million.The good news is that AI stocks recovered, and then some. They surged to record highs as Western models kept improving and held their lead, quashing fears that cheaper Chinese models could catch up. For a while, that justified the massive capital expenditure the West had committed to.

Most AI models are judged on how well they answer a question, write a Python script, or pass an exam. Chip design is a different beast. It is a gruelling, multi-step engineering process. By completing all of it autonomously over 48 hours with no human intervention, Impressive as it is, this is still far from the end for the two EDA giants. The demo leaned on the Nangate 45-nanometer Open Cell Library. In the semiconductor world, 45nm is ancient history. It is the node that built consumer chips back in 2007 and 2008.

Modern AI accelerators are fabricated on cutting-edge 3nm or 2nm nodes. At 45nm, the physics of chip design are relatively straightforward and forgiving. At 3nm, engineers wrestle with extreme ultraviolet (EUV) lithography, quantum tunnelling, and severe thermal density. Designing a 45nm chip autonomously does not prove an AI can handle the staggering multi-physics complexity of modern frontier silicon. At 3nm and 2nm, Cadence and Synopsys software is a necessity, not an option.