$Taiwan Semiconductor Manufacturing(TSM)$
Who says TSMC's silicon photonics uses a 3-nanometer process? COUPE is clearly 65 nanometers. The 3-nanometer process mentioned in the news is probably related to the packaging of a 3-nanometer GPU chiplet. Silicon photonics doesn't require such a small manufacturing process, especially when the electronic chip and the photonic chip are separate. Monolithic integration would be beneficial for the electronic chip. Currently, Global Foundry is the only one that supports a 45-nanometer integrated electro-optic silicon photonics process.
Disclaimer: Investing carries risk. This is not financial advice. The above content should not be regarded as an offer, recommendation, or solicitation on acquiring or disposing of any financial products, any associated discussions, comments, or posts by author or other users should not be considered as such either. It is solely for general information purpose only, which does not consider your own investment objectives, financial situations or needs. TTM assumes no responsibility or warranty for the accuracy and completeness of the information, investors should do their own research and may seek professional advice before investing.
